The present invention relates to data storage, and more specifically to RAM storage cells.
Many different types of data storage are used in various parts of a computer system. Non-volatile memory retains its data even when power is not applied. Volatile memory requires energy to retain its data. Two types of volatile memory are static and dynamic random-access memory (RAM).
RAM data storage is memory in which any cell can be randomly accessed for read and write by inputting the coordinates of that cell on the address pin. Basic RAM architecture can include inputs, outputs, addresses, read control, write control, and data storage. The basic cell stores two well defined states in a repeatedly accessible location.
Capacitors and latches are commonly used as RAM storage cells. These types of storage are susceptible to instability under certain circumstances, namely on read (when the stored data is accessed) and on standby (when the stored data is not being accessed).
Background: Standby Instability
Cells that use capacitors are normally unstable on standby, since charge stored in capacitors tends to leak away with time. The data stored in capacitors must therefore be periodically refreshed. Refreshing data consists sensing the state stored in the cell (1 or 0) and writing that state back to the cell, thus restoring the memory cell to its original state. Periodic refresh is a source of power consumption in standby. Storage cells that store charge on a capacitor and require refresh are termed dynamic RAM, or DRAM.
In addition to requiring periodic refresh, the sensing or reading of information in a DRAM cell upsets the storage state, destroying the stored information. The information must be restored to the cell (usually by writing the state back into the cell) within the read cycle.
Latches use bistable flipflops to store data. Typical storage cells are shown in FIGS. 1a-1c. FIG. 1a shows a 6T SRAM cell with PMOS load devices. Data are stored as voltage levels with the two sides of the flipflop in opposite voltage states. The load devices offset charge leakage at the drains of the driver and access transistors. FIG. 1b shows a similar cell that uses resistors rather than transistors. This permits reduction in cell size because the resistors can be stacked on top of the cell, but also has higher leakage in standby, trading performance for cost. FIG. 1c shows a standard 4T SRAM storage cell. This cell uses two PMOS transistors as pass transistors and two NMOS transistors as drive transistors.
Data storage will be discussed with reference to FIG. 1c. The storage states are determined by the relative potential between the two nodes, A and B. When node A is high, transistor 102 conducts, which grounds node B. Grounding node B turns off transistor 104, which maintains the high potential at A.
Transistors experience leakage due to subthreshold currents even when the transistor is off. To maintain high node voltage, the on p-channel transistor (6T cell), resistor (4T-2R cell), or subthreshold current of the pass transistor (4T cell) must be enough to counter the subthreshold current of the off n-channel drive transistor plus any other leakage current at that node. For the 4T cell, it may be necessary to lower the wordline voltage. This will maintain the stored high voltage state by increasing the p-channel pass gate transistor subthreshold current. It is desirable to minimize the current required to maintain the stored voltage state. For DRAM, where the stored voltage is maintained by charge stored on a capacitor, the leakage or subthreshold currents limit the time for which the stored voltage can be maintained. The DRAM cell must therefore be periodically refreshed through a read and write-back to the cell.
Background: Read Instability
A bit stored in a memory cell is accessed by its row and column address. FIG. 2 shows a RAM storage architecture. The row decoder 202 selects a row address from the N rows. All M cells on that row, or wordline, are activated. The column decoder 204 then selects a subset of the M bits for output. There may be one sense amp per column, and the column select chooses from the output of the M sense amps. Alternatively, there may be fewer sense amps than columns, and the column decode selects which columns are to be connected to the sense amps. If there is more than one sense amp, the column select may further select among the outputs of the multiple sense amps. In FIG. 2, the sense amplifier 208 detects the voltage differential between the two bitlines of the selected column, amplifies this voltage difference, and sends the data out of the array. A read-write control circuit 206 controls Input and Output.
In a cell with PMOS pass transistors, the wordlines are maintained high to keep the cell isolated from the bitline. Keeping the wordline high keeps the PMOS transistor from conducting. When a wordline is accessed, its voltage is lowered, which turns on the pass transistors. This connects all cells in that wordline to the associated bitlines. PMOS pass transistors 106, 108 are shown in FIG. 1c. 
The state of every cell on that wordline is potentially disturbed at this point because of the precharge on the bitlines. Referring back to FIG. 1c, assume that node B is in a low potential state, and node A is high. If the bitlines are precharged high, the low side of the storage cell must pull that bitline low to establish a differential voltage on the bitlines for detection. At the same time, the charge on the bitline will tend to pull node B high.
In a perfectly balanced case, a differential voltage between node A and node B will be maintained and the memory state will be retained. However, if there are asymmetries in the cell that prefer the state where node A is low, the memory cell may be upset when accessed. The amount of asymmetry that can be tolerated without upset of the memory cell when accessed is referred to as the noise margin. The magnitude of the noise margin is affected by the strength (drive current capacity) of the drive transistor relative to the strength of the pass transistor in the memory cell. The stronger the drive transistor relative to the pass transistor, the greater the noise margin.
It should be noted that even if the memory is upset on access, there will be an initial differential voltage imposed on the bitlines reflecting the original state of the accessed memory cell. One design criterion for SRAM cells has been that they have sufficient noise margin to not upset on access for anticipated ranges of asymmetry at expected operating conditions. In contrast, memory is expected to be lost on access of DRAM cells. For DRAM cells the initial voltage imposed on the bitline is detected. The detected state of the accessed memory cell is subsequently written back into the accessed cell, restoring the original state.
Background: Cell Beta
Many important features in a memory cell depend at least in part on the dimensions of the transistors. A transistor is formed on a chip wherever a polysilicon path crosses a diffusion path, as shown in FIG. 3. The leakage or off-state current of a transistor is proportional to W. The leakage current dependence on L is more complex, but generally leakage decreases with increases of L from the minimum design values. Thus the ratio of W to L determines both the drive and off-state capacity of the transistor. As this ratio increases (i.e., as W increases or as L decreases), the drive capacity increases. This ratio is referred to as W/L.
In SRAM storage cells, the operation and stability of the cell in standby and on read is influenced by these ratios. The ratio between the drive capacity of the drive transistors to the drive capacity of the pass transistors is called the cell beta. For the 4T cell, if cell beta is designed to be high (i.e., the drive transistors have greater drive and leakage current capacity than the pass transistors), then the cell will be unstable on standby, but stable on read. Conversely, if the 4T cell beta is designed to be low (meaning the drive transistors have less drive and leakage capacity than the pass transistors) then standby stability is achieved, and read stability is lowered.
The possibility of upset on read is an increasing problem with scaling as threshold voltages are lowered and as exact matching of the transistors becomes more difficult. As device sizes are scaled down, the amount of dopant within the transistor volume decreases. As doping decreases, the margin of error decreases, since a small variation in the number of doping atoms becomes more significant.
For a 6T cell, there is a similar memory trade-off of noise margin, trip voltage, and read current. For a given cell area, increasing the noise margin requires lowering the read current or making the write more difficult, or both.
Instability on read and standby causes conflicting design considerations in RAM storage. Various approaches balancing these considerations have been used. For instance, a four transistor (4T) SRAM cell disclosed by NEC Corporation uses a flipflop and two p-channel pass transistors. The n-channel drive transistors are given a higher threshold voltage to ensure the subthreshold current for the drive transistor is less than that of the pass transistors. This results in standby stability and read stability (at sufficiently high operating voltage), but with reduced noise margin and increased process cost (namely a VT implant). The size of VT in this approach is limited because of the requirement of read stability. The requirement of read stability also limits the minimum value for storage voltage. Other proposed designs do away with the VT implant, and instead lower the wordline voltage during standby to maintain the memory state. This relaxes the requirements on pass and drive transistors, allowing them to be better optimized for noise margin, but with greater power dissipation on standby. A lowering of all wordlines during a portion of the active cycle may also be required to maintain memory. There is thus a need in the art for a memory cell that uses standard processes, has low voltage operation, and that couples low standby current with stability in standby.
SRAM with Write-Back on Read
The present application discloses a memory system that is stable on standby but may upset on read. Read stability is sacrificed to get standby stability. This trade is advantageous because it minimizes power requirements on standby. The memory system includes a write-back in the read cycle to compensate for the read instability.
Even when the SRAM cell is upset on read, the cell imposes an initial differential on the bitlines in accordance with the stored data. This initial differential will be lost after the cell upsets. The innovative memory system senses the stored state even though the cell is subject to upset and writes that state back to the cell during or immediately after the read cycle.
When implemented with a 4T cell, the balance of the leakage current can be improved by design of the W/L ratios of the pass and drive transistors. The pass transistors are made wider and shorter than the drive transistors, which increases the subthreshold current of the pass transistor relative to that of the drive transistor. This decreases beta and makes the cell more stable in standby, but less stable on read.
The sacrifice of read stability also raises the trip voltage (the voltage that must be obtained on the bitlines to write into the cell). This creates a greater write margin for the cell. Increased standby stability also allows a larger imbalance to exist in the cell and still maintain proper operation.
Another inventive aspect of the present application involves increasing standby stability by using a VT implant. Previous limits to the VTN because of read stability requirements are alleviated by incorporating a write-back. This also allows a lower storage voltage to be used.
When implemented with a 6T cell, the noise margin of the cell can be reduced to allow increased read current or to increase margin for writing into the cell.
The disclosed innovations, in various embodiments, provide one or more of at least the following advantages:
compact cell with standard process;
good operation at low voltage;
standby stability;
low standby current;
greater write margin.